Tronics Microsystems offers a new SOI technology on MPW

Tronics Microsystems is now offering a new technology of 60µm SOI High Aspect Ratio Micromachining featuring an hermetic Wafer Level Packaging on a MPW service. This is the first industrial technology of this type and it is now available on low-cost Multi-Project Wafer prototyping service.

Universities and companies have access to a design rules manual and associated Design kit based on Coventor tool suite (both sent on demand) to design structures and components of their own.

Prices:

Prices vary based on the number of designs submitted for the same run. Separate pricing is offered for universities and research labs.

For each location, Tronics Microsystems delivers 20 dies, released and protected by an hermetic silicon wafer level package.

Price/location/run     
Corporate
     
Academic
   
For 1 location
7,500 €
4,500 €
For 2-3 locations
6,500 €
3,500 €
For 4-5 locations
5,500 €
3,000 €
 

Chip characteristics:   

  • Die size: 8 x 7 mm2   
  • Active area: 7.5 x 6.5 mm2   
  • Hermetic silicon cap   
  • Structures released   
  • Up to 24 pads or openings on the cap

Planning runs:

                                                                                                     
Run     
Design submission
(GDSII format)     
Delivery
(20 chips)    
N
Jan. 1
April 31
N+1
May 1
Aug. 31
N+2
Sept. 1
Dec. 31